CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n⁺-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W_B, (and hence on f_Tmax, since f_T∝1/ W_B²) and strong dependence on the effective base width W_B(eff), where W_B(eff) nearly equals the distance between the emitter and the n⁺ collector, d_E-C. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d_E-C. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET