Title :
A high-performance 0.25-μm CMOS technology. I. Design and characterization
Author :
Chang, Wen-Hsing ; Davari, Bijan ; Wordeman, Matthew R. ; Taur, Yuan ; Hsu, Charles Ching-Hsiang ; Rodriguez, M.D.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
4/1/1992 12:00:00 AM
Abstract :
A high-performance 0.25-μm-channel CMOS technology is designed and characterized. The technology utilizes n+ polysilicon gates on nFETs and p+ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, Cw=0.2 pF) delay per stage of 280 ps at Weff/Leff=15 μm/0.25 μm, which is a 1.7× improvement over 0.5-μm CMOS technology. At a channel length of 0.18 μm, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed
Keywords :
CMOS integrated circuits; delays; integrated circuit technology; logic gates; 0.18 micron; 0.2 pF; 0.25 micron; 15 micron; 185 ps; 280 ps; 38 ps; 7 nm; CMOS stage delay; CMOS technology; NAND; Si; Si:As-Si:B; abrupt source drain junctions; design; gate oxide thickness; high-performance; high-speed operation; loaded NAND ring oscillators; loaded ring oscillator; n+ polysilicon gates; nFETs; p+ polysilicon gates; pFETs; reduced power supply voltage; surface channel devices; unloaded inverter; CMOS technology; Circuits; Delay; Electrical resistance measurement; Inverters; Power engineering and energy; Power supplies; Reliability engineering; Ring oscillators; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
