Title :
A high-performance 0.25-μm CMOS technology. II. Technology
Author :
Davari, Bijan ; Chang, Wen-Hsing ; Petrillo, K.E. ; Wong, C.Y. ; Moy, Dan ; Taur, Yuan ; Wordeman, Matthew R. ; Sun, Jack Yuan-Chen ; Hsu, Charles Ching-Hsiang ; Polcari, Michael R.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
4/1/1992 12:00:00 AM
Abstract :
For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25-μm CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi2) process. The TiSi2 thickness is reduced to maintain low leakage and low contact resistance for the shallow S/D junctions. The gate level with 0.4-μm physical length is defined using optical lithography with a contrast enhanced layer (CEL) resist system
Keywords :
CMOS integrated circuits; contact resistance; integrated circuit technology; photolithography; 0.25 micron; 2.5 V; TiSi2 thickness; abrupt profiles; contrast enhanced layer resist system; device series resistance; dual poly gates; gate to source/drain overlap capacitance; high performance selectively scaled CMOS technology; low contact resistance; low leakage; operating voltage; optical lithography; shallow junctions; source/drain sheet resistance; thin salicide; Boron; CMOS process; CMOS technology; Delay; Implants; Lithography; Resists; Sheet materials; Surfaces; Tungsten;
Journal_Title :
Electron Devices, IEEE Transactions on
