Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors

This article presents design for testability and self-testing approaches for bit-serial signal processors??specifically, for an integrated circuit consisting of bit-serial data paths whose integration level requires approximately 120,000 transistors packaged in a 68-pin chip carrier. The bit-serial architecture lends itself to a scan-type approach for functional testing with minimum design modification. The functional verification testing requires less than one percent additional hardware, plus a minimum of four additional I/O package pins. Although less straightforward, self-testing was still accomplished without execessive penalties. A potential solution to the problem of data integrity of the interchip communication lines required only a minimum amount of hardware and additional I/O pins.