Fully balanced CMOS current-mode circuits

Author

Zele, Rajesh H. ; Allstot, David J. ; Fiez, Terri S.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

28

Issue

5

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

569

Lastpage

575

Abstract

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V_dd 5 V

Keywords

CMOS integrated circuits; active filters; amplifiers; ladder networks; linear integrated circuits; low-pass filters; 128 kHz; 14 mW; 2 micron; 5 V; 5 kHz; CMOS current-mode circuits; analog signal processing applications; charge-injection effects; clock-feedthrough; current mirror/amplifier; first-order cancellation; five-pole Chebyshev filter; fully balanced circuit topology; ladder filters; low-pass; n-well CMOS process; p-well CMOS process; switched-current integrator; Band pass filters; CMOS process; Circuit topology; Clocks; Current mode circuits; Mirrors; Signal processing; Signal sampling; Switches; Total harmonic distortion;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.229398

Filename

229398