Title :
A high-performance data path for synthesizing DSP kernels
Author :
Galanis, Michalis D. ; Theodoridis, George ; Tragoudas, Spyros ; Goutis, Costas E.
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Patras, Rio
fDate :
6/1/2006 12:00:00 AM
Abstract :
A high-performance data path to implement digital signal processing (DSP) kernels is introduced in this paper. The data path is realized by a flexible computational component (FCC), which is a pure combinational circuit and it can implement any 2 times 2 template (cluster) of primitive resources. Thus, the data path´s performance benefits from the intracomponent chaining of operations. Due to the flexible structure of the FCC, the data path is implemented by a small number of such components. This allows for direct connections among FCCs and for exploiting intercomponent chaining, which further improves performance. Due to the universality and flexibility of the FCC, simple and efficient algorithms perform scheduling and binding of the data flow graph (DFG). DSP benchmarks synthesized with the FCC data path method show significant performance improvements when compared with template-based data path designs. Detailed results on execution time, FCC utilization, and area are presented
Keywords :
combinational circuits; data flow graphs; digital signal processing chips; scheduling; DSP kernels; combinational circuit; data flow graph; digital signal processing; flexible computational component; high-performance data path; scheduling; template units; Circuit synthesis; Combinational circuits; Digital signal processing; FCC; Flexible structures; Flow graphs; Kernel; Scheduling algorithm; Signal processing algorithms; Signal synthesis; Binding; chaining; high-performance data path; scheduling; template units;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.855965