DocumentCode :
928898
Title :
Reducing clock skew variability via crosslinks
Author :
Rajaram, Anand ; Hu, Jiang ; Mahapatra, Rabi
Author_Institution :
Texas Instrum. Inc., Dallas, TX
Volume :
25
Issue :
6
fYear :
2006
fDate :
6/1/2006 12:00:00 AM
Firstpage :
1176
Lastpage :
1182
Abstract :
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amounts of wirelength. This paper suggests to construct a low-cost nontree clock network by inserting crosslinks in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, this paper proposes two link insertion schemes that can quickly convert a clock tree to a nontree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated nontree delay computation is circumvented. Further, they can be applied to the recently popular nonzero skew routing easily. The effectiveness of the proposed techniques has been validated through SPICE-based Monte Carlo simulations
Keywords :
VLSI; clocks; tree codes; SPICE-based Monte Carlo simulations; VLSI; clock skew variability; crosslinks; nontree clock network; very large scale integration; Clocks; Delay; Energy efficiency; Land surface temperature; Manufacturing processes; Microprocessors; Routing; Semiconductor device noise; Signal design; Very large scale integration; Clock; skew; variability; very large scale integration (VLSI);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.855928
Filename :
1629151
Link To Document :
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