DocumentCode :
928913
Title :
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model
Author :
Zhang, Lizheng ; Chen, Weijen ; Hu, Yuhen ; Chen, Charlie Chung-Ping
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Wisconsin, Madison, WI
Volume :
25
Issue :
6
fYear :
2006
fDate :
6/1/2006 12:00:00 AM
Firstpage :
1183
Lastpage :
1191
Abstract :
An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this paper, which features 1) a conditional linear approximation method of the MAX/MIN timing operator, 2) an extended canonical representation of correlated timing variables, and 3) a variation pruning method that facilitates intelligent tradeoff between simulation time and accuracy of simulation result. A special design focus of the proposed algorithm is on the propagation of the statistical correlation among timing variables through nonlinear circuit elements. The proposed algorithm distinguishes itself from existing block-based SSTA algorithms in that it not only deals with correlations due to dependence on global variation factors but also correlations due to signal propagation path reconvergence. Tested with the International Symposium on Circuits and Systems (ISCAS) benchmark suites, the proposed algorithm has demonstrated very satisfactory performance in terms of both accuracy and running time. Compared with Monte-Carlo-based statistical timing simulation, the output probability distribution got from the proposed algorithm is within 1.5% estimation error while a 350 times speed-up is achieved over a circuit with 5355 gates
Keywords :
VLSI; approximation theory; network analysis; statistical analysis; timing circuits; VLSI; circuit performance analysis; conditional linear MAX/MIN approximation; extended canonical timing model; nonlinear circuit elements; process variation; signal propagation path reconvergence; statistical static timing analysis; very large scale integration; Algorithm design and analysis; Analytical models; Approximation algorithms; Circuit simulation; Circuit testing; Circuits and systems; Linear approximation; Nonlinear circuits; System testing; Timing; Circuit performance analysis; extended canonical timing model; path reconvergence; process variation; statistical static timing analysis; very large scale integration (VLSI);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.855979
Filename :
1629152
Link To Document :
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