DocumentCode :
929227
Title :
Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications
Author :
Chen, Nansen ; Lin, Hongchin ; Lai, Jeng-Yuan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
Volume :
29
Issue :
2
fYear :
2006
fDate :
5/1/2006 12:00:00 AM
Firstpage :
364
Lastpage :
371
Abstract :
Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3π models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.
Keywords :
DRAM chips; SPICE; SRAM chips; ball grid arrays; chip scale packaging; electromagnetic field theory; equivalent circuits; heat sinks; high-speed integrated circuits; lead; transient analysis; 3D full-wave electromagnetic field solver; 800 Mbit/s; COHS-LF packages; Pb; SPICE simulator tests; chip encapsulation structure; chip-on-heat sink leadframe package; chip-scale packages; double data rate SDRAM; electrical performance; equivalent circuit model; high-speed integrated circuit; parasitic effects; power consumption; signal bandwidth; thermal performance; transient analysis; Bandwidth; Chip scale packaging; Data communication; Electronics packaging; Encapsulation; Energy consumption; High speed integrated circuits; Integrated circuit packaging; SDRAM; Time to market; Ball grid array (BGA); SPICE; chip-on-heat sink leadframe (COHS-LF); crosstalk; exposed heat sink; rise time; thin small outline packages (TSOPs);
fLanguage :
English
Journal_Title :
Advanced Packaging, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3323
Type :
jour
DOI :
10.1109/TADVP.2006.874698
Filename :
1629180
Link To Document :
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