A bit-serial VLSI architecture for generating moments in real-time

In computer vision and image processing, the high degree of parallelism and pipelining of algorithms is often obstructed by the raster-scan I/O constraint and the information growing property of multiresolution structures. The approach of formulating algorithms in the pyramid structure as a binary tree structure, and mapping the binary tree structure into a linear pipelined array of 2logN levels for N×N images using a first-in, first-out technique (FIFO) to emulate the tree connections is proposed. It turns out that several geometric feature extraction algorithms such as moment generation can be represented in this scheme so that the inherent information growing of the algorithms enables the exploitation of bit-level concurrency in the architectural design. Consequently, the design of pipelined processor at each level is significantly simplified using bit-serial arithmetic, and this VLSI architecture is capable of generating moments concurrently in real-time