• DocumentCode
    929705
  • Title

    VLSI implementation of a 5-trit full adder

  • Author

    Mouftah, H.T. ; Garba, A.I.

  • Author_Institution
    Queen´´s University, Department of Electrical Engineering, Kingston, Canada
  • Volume
    131
  • Issue
    5
  • fYear
    1984
  • fDate
    10/1/1984 12:00:00 AM
  • Firstpage
    214
  • Lastpage
    220
  • Abstract
    The design and implementation of a 5-trit full adder is presented. Only enhancement-type CMOS transistors are used in the circuitry. The CMOS chip layout of the ternary full adder is presented, with the computer simulation results for all the circuits.
  • Keywords
    adders; digital arithmetic; field effect integrated circuits; integrated logic circuits; large scale integration; logic design; ternary logic; 5-trit full adder; CMOS chip layout; VLSI implementation; computer simulation; design methodology; digital IC; digital arithmetic; ternary full adder; three-valued logic;
  • fLanguage
    English
  • Journal_Title
    Electronic Circuits and Systems, IEE Proceedings G
  • Publisher
    iet
  • ISSN
    0143-7089
  • Type

    jour

  • DOI
    10.1049/ip-g-1:19840040
  • Filename
    4646202
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=929705