Title :
Restructuring and logic minimization for testable PLA
Author :
Hwang, Gwo-Haur ; Shen, Wen-Zen
Author_Institution :
Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
4/1/1993 12:00:00 AM
Abstract :
The untestability cube-number product (UCP), a testability measure that can accurately indicate the extra logic needed in testable programmable logic arrays (PLAs), is discussed. Two UCP-based PLA synthesis algorithms are developed. The first one is a restructuring algorithm named REST, and the other is a logic minimizer for testable PLA named LMTPLA. REST can make the restructured PLA testable by taking less extra hardware. LMTPLA is based on EXPRESSO-II and REST. It can consider the testability at the logic minimization process. In order to minimize UCP as well as the number of product terms, four strategies are developed: deleting the cubes with poor testability and reserving the cubes with good testability; giving up the primes, if necessary: partitioning the more untestable cubes into smaller cubes; and deleting the procedures which are useless in LMTPLA. REST and LMTPLA have been implemented on SUN4/260 in C language. For 40 benchmark circuits, the hardware overheads required are reduced by about 30-40%
Keywords :
circuit CAD; logic CAD; logic arrays; logic testing; minimisation of switching nets; C language; EXPRESSO-II; LMTPLA; PLA synthesis algorithms; REST; SUN4/260; logic minimization; programmable logic arrays; restructuring algorithm; testability measure; testable PLA; untestability cube-number product; Circuit faults; Circuit testing; Decoding; Hardware; Logic arrays; Logic design; Logic testing; Minimization; Programmable logic arrays; Shift registers;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on