DocumentCode :
930068
Title :
Test generation to minimize error masking
Author :
Edirisooriya, Geetani ; Robinson, John P.
Author_Institution :
Motorola Computer Group, Tempe, AZ, USA
Volume :
12
Issue :
4
fYear :
1993
fDate :
4/1/1993 12:00:00 AM
Firstpage :
540
Lastpage :
549
Abstract :
A unified scheme for test-pattern generation and output compaction using circuit-specific information is presented. It is shown that partial control over test-pattern sequence can give zero aliasing in single-output circuits and reduced aliasing in multiple-output circuits. The exact aliasing probability is obtained for multiple-output circuits under the independent bit error model for any test length. The aliasing probability for multiple-output circuits of this scheme is independent of the feedback polynomial of the multiple-input shift register (MISR). This method reduces aliasing considerably without increasing the length of the MISR by having a simple quotient detector. The approach is applied to benchmark circuits to show the applicability of the scheme to a given combinational circuit
Keywords :
combinatorial circuits; logic design; logic testing; probability; aliasing probability; bit error model; circuit-specific information; combinational circuit; error masking minimisation; multiple-input shift register; multiple-output circuits; output compaction; output response analyser; quotient detector; single-output circuits; test-pattern generation; test-pattern sequence; unified scheme; zero aliasing; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Compaction; Fault detection; Performance analysis; Performance evaluation; Test pattern generators;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.229737
Filename :
229737
Link To Document :
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