Statistical degradation analysis of digital CMOS IC´s

Author

Rangavajjhala, Venkata S. ; Bhuva, Bharat L. ; Kerns, Sherra E.

Author_Institution

Cirrus Logic Inc., Milpitas, CA, USA

Volume

12

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

837

Lastpage

844

Abstract

A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability

Keywords

CMOS integrated circuits; circuit analysis computing; digital integrated circuits; failure analysis; integrated logic circuits; statistical analysis; degradation analysis; digital CMOS integrated circuits; environmental effects; fabrication process fluctuations; parameter variations; performance failure; statistical analysis; statistical switch-level simulator; Analytical models; CMOS digital integrated circuits; CMOS integrated circuits; Circuit simulation; Computational modeling; Degradation; Fabrication; Fluctuations; Statistical analysis; Switching circuits;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.229759

Filename

229759