DocumentCode
930255
Title
On the multiple-fault testability of generalized counters
Author
Vergis, Anastasios
Author_Institution
Minnesota Univ., Minneapolis, MN, USA
Volume
12
Issue
6
fYear
1993
fDate
6/1/1993 12:00:00 AM
Firstpage
905
Lastpage
909
Abstract
It is shown that any generalized counter of full-adder cells is testable for multiple faults with a test set of size proportional to the number of cells. Any number of cells can be faulty in any way, as long as the faults are permanent, the cells remain combinational, and no signal values other than 0 and 1 are generated
Keywords
counting circuits; logic testing; full-adder cells; generalized counters; multiple-fault testability; Circuit faults; Circuit testing; Computer science; Counting circuits; Helium; Logic arrays; Logic testing; Signal generators; Vectors; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.229765
Filename
229765
Link To Document