DocumentCode :
930948
Title :
Analysis of coupling noise between adjacent bit lines in megabit DRAMs
Author :
Konishi, Yasuhiro ; Kumanoya, Masaki ; Yamasaki, Hiroyuki ; Dosaka, Katsumi ; Yoshihara, Tsutomu
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
Volume :
24
Issue :
1
fYear :
1989
Firstpage :
35
Lastpage :
42
Abstract :
Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the work-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions the more serious both the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because its thickness and layer position.<>
Keywords :
VLSI; field effect integrated circuits; integrated circuit technology; integrated memory circuits; random-access storage; Al bit line; READ-signal degradation; adjacent bit lines; bit-line coupling capacitance; bit-line materials; bit-line-to-bit-line capacitance; charge conservation model; disturbance in sensing operation; layer position; megabit DRAMs; noise mechanisms; passivation materials; polycide bit-line structure; simulation of sensing operation; soft error tests; total bit-line capacitance; types of noise effects; Artificial intelligence; Capacitance measurement; Degradation; Error analysis; Life estimation; Passivation; Performance evaluation; Random access memory; Signal to noise ratio; Testing;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.16299
Filename :
16299
Link To Document :
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