A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

Author

Nishimura, Yasumasa ; Hamada, Mitsuhiro ; Hidaka, Hideto ; Ozaki, Hideyuki ; Fujishima, Kazuyasu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

24

Issue

1

fYear

1989

Firstpage

43

Lastpage

49

Abstract

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test.<>

Keywords

VLSI; automatic testing; integrated circuit technology; integrated circuit testing; integrated memory circuits; random-access storage; redundancy; 1 Mbit; 1-Mbit DRAM; BIST; MBT; RFLG; efficient redundancy test; hardware option; memory LSI tester; multibit test mode; program development time; redundancy architecture; redundancy flag; redundancy test-time reduction technique; throughput increase; yield improvement; Circuit synthesis; Circuit testing; Costs; Data buses; Decoding; Laboratories; Large scale integration; Production; Random access memory; Redundancy;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16300

Filename

16300