DocumentCode :
931298
Title :
Optimised bit level systolic array for convolution
Author :
McCanny, J.V. ; McWhirter, J.G. ; Wood, K.
Author_Institution :
Royal Signals & Radar Establishment, Malvern, UK
Volume :
131
Issue :
6
fYear :
1984
fDate :
10/1/1984 12:00:00 AM
Firstpage :
632
Lastpage :
637
Abstract :
A bit level systolic array for computing the convolution operation is described. The circuit in question is highly regular and ideally suited to VLSI chip design. It is also optimised in the sense that all the cells contribute to the computation on each clock cycle. This makes the array almost four times more efficient than one which was previously described.
Keywords :
cellular arrays; integrated logic circuits; large scale integration; logic CAD; optimisation; signal processing; VLSI chip design; bit level systolic array; clock cycle; convolution; logic IC computer-aided design; optimisation;
fLanguage :
English
Journal_Title :
Communications, Radar and Signal Processing, IEE Proceedings F
Publisher :
iet
ISSN :
0143-7070
Type :
jour
DOI :
10.1049/ip-f-1.1984.0097
Filename :
4646364
Link To Document :
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