Systolic architectures for the manipulator inertia matrix

Systolic architectures consisting of 1, N, and N(N+1)/2 processors are presented for computing the manipulator inertia matrix. A VLSI-based robotics processor which is under development is the fundamental component of the architecture. Its major elements are a 32-bit floating-point multiplier, a 32-bit floating-point adder, a triple-port memory, and four I/O ports for external communication which are interconnected to facilitate implementation of robotics operations. The algorithm used is based on recursive computation of the inertial parameters of sets of composite rigid bodies and is programmed to exploit any inherent parallelism. Good results are obtained for the N-processor and N(N +1)/2-processor configurations that give a compute-time delay of O( N). I/O time and idle time due to processor synchronization as well as CPU utilization and on-chip memory size are fully included in the evaluation and indicate the feasibility and effectiveness of the design