Title :
A CMOS model for computer-aided circuit analysis and design
Author :
Roberts, James W. ; Chamberlain, Savvas G.
Author_Institution :
Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
Abstract :
An equivalent circuit model to simulate the current-voltage behavior of CMOS transistors is discussed. This model can simulate the full range of complementary MOSFET operation and can handle latchup at the circuit analysis level. Using effective injection efficiencies a switching criterion and a method of solution for a four parasitic bipolar transistor system have been developed and incorporated. The configuration of the CMOS device is computed from data submitted by the user. This includes well depth, MOSFET separation, doping levels, minority-carrier lifetime, substrate bypass resistors, the option to float either or both substrates, and bias conditions. The model can be used alone or incorporated into existing computer-aided-design programs for analysis of circuits which contain CMOS components.<>
Keywords :
CMOS integrated circuits; circuit CAD; equivalent circuits; semiconductor device models; CMOS model; CMOS transistors; MOSFET separation; bias conditions; circuit CAD; circuit analysis level; complementary MOSFET operation; computer-aided circuit analysis; computer-aided-design programs; current-voltage behavior; doping levels; equivalent circuit model; four parasitic bipolar transistor system; injection efficiencies; latchup; method of solution; minority-carrier lifetime; substrate bypass resistors; switching criterion; well depth; Analytical models; Bipolar transistors; Circuit analysis; Circuit analysis computing; Circuit simulation; Computational modeling; Doping; Equivalent circuits; MOSFET circuits; Semiconductor device modeling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
