Title :
Design methodology for self-timed VLSI systems
Author :
Lister, P.F. ; Alhelwani, A.M.
Author_Institution :
University of Sussex, School of Engineering and Applied Sciences, Brighton, UK
fDate :
1/1/1985 12:00:00 AM
Abstract :
A design methodology for self-timed VLSI systems is proposed. This includes a language for describing algorithmic behaviour which is based on the data-flow concept. A subclass of Petri nets is introduced to model the designed system, and a refinement technique is presented that allows for the synthesis of correct-by-construction systems. Finally, a systematic means for implementing the design is given.
Keywords :
VLSI; directed graphs; logic design; parallel processing; specification languages; Petri nets; algorithmic-behavioural description language; correct-by-construction systems; data-flow concept; design methodology; refinement technique; self-timed VLSI systems; subclass;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
DOI :
10.1049/ip-e:19850003
