Analog CMOS deterministic Boltzmann circuits

CMOS circuits implementing an analog neural network (ANN) with on-chip deterministic Boltzmann learning (DBL) and capacitive synaptic weight storage have been designed, fabricated, and tested. Weights are refreshed by periodic repetition of the training data. The circuits were used to build a 12-neuron, 132-synapse ANN that performed well in a variety of learning experiments, including a 36-input to 4-output mapping problem. Adaptive systems such as those described here can compensate for imperfections in the components from which they are constructed and therefore can be built using simple silicon area-efficient analog circuits. The test results indicate that deterministic Boltzmann ANNs can be implemented efficiently using analog CMOS circuitry