A 3.3-V 800-nVrms noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

A 3.3-V CMOS low-noise gain-programmable microphone amplifier with a high-impedance balanced input is presented. The preamplifier allows gains from 20 to 35 dB to be set by software control in 1-dB steps with 0.05-dB accuracy. Typical measured V_OS is 0.8 mV, V_OS drift is 1 μV/C, input-referred p-weighted noise is 0.8 μV _rms and total harmonic distortion (THD) is -70 dB. The active area is about 350 mils², and power consumption is 1.7 mW at 3.3-V supply and 2.9 mW at 5-V supply. These results have been obtained through an intensive use of the yield modeling technique for yield-performance optimization during the design phase, and by applying a common-centroid cross-coupled strategy to the layout of all the ideally matched MOS transistors in the input stage