DocumentCode :
931949
Title :
Synthesis method for field programmable gate arrays
Author :
Sangiovanni-Vincentelli, Alberto ; Gamal, Abbas El ; Rose, Jonathan
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume :
81
Issue :
7
fYear :
1993
fDate :
7/1/1993 12:00:00 AM
Firstpage :
1057
Lastpage :
1083
Abstract :
Logic synthesis algorithms and methods for field-programmable gate arrays (FPGAs) are reviewed. The three most popular types of FPGA architectures are considered, namely, those using logic blocks based on lookup-tables, multiplexers, and wide AND/OR arrays, respectively. The emphasis is on tools that attempt to minimize the area of the combinational logic part of a design, since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs
Keywords :
application specific integrated circuits; circuit CAD; logic CAD; logic arrays; FPGA architectures; combinational logic part; field programmable gate arrays; logic synthesis algorithms; lookup-tables; multiplexers; sequential part; wide AND/OR arrays; Application specific integrated circuits; Design automation; Design optimization; Field programmable gate arrays; Integrated circuit synthesis; Libraries; Logic arrays; Logic design; Multiplexing; Process design;
fLanguage :
English
Journal_Title :
Proceedings of the IEEE
Publisher :
ieee
ISSN :
0018-9219
Type :
jour
DOI :
10.1109/5.231344
Filename :
231344
Link To Document :
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