An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3,2n+1,2n-1,2n+3)

In this paper, we present a new four-moduli set (2ⁿ-3,2ⁿ+1,2ⁿ-1,2ⁿ+3) and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set include 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic operations; and 4) flexible moduli set selection. According to the relation between the proposed moduli, the divide-and-conquer technique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b (n=3), our architecture has about 47% saving in hardware cost and 40% saving in critical delay compared to the last work.