A memory-controlled crosspoint switch using E-beam restructuring

Author

Fried, Jeff ; Daly, Elizabeth ; Lyszczarz, Ted ; Copperman, M.

Author_Institution

GTE Labs., Waltham, MA, USA

Volume

24

Issue

1

fYear

1989

Firstpage

183

Lastpage

187

Abstract

The design and yield analysis of a yield-enhanced crosspoint switch chip capable of operating at broadband rates is described. The chip, which is a prototype of a wafer-scale system, incorporates three levels of redundancy in order to increase the yield and the fault tolerance of the system. E-beam-programmable interconnect structures, using floating-gate FETs, implement customization and yield enhancement. A scanning-electron-beam lithography system is used to program these structures. An analysis of a wafer-scale crosspoint switch design extrapolated from the chip design indicates that an 80*75 array could be built with >90% yield.<>

Keywords

CMOS integrated circuits; VLSI; electron beam lithography; electronic switching systems; semiconductor switches; time division multiplexing; CMOS; E-beam restructuring; E-beam-programmable interconnect structures; WSI; broadband rates; customization; fault tolerance; floating-gate FETs; memory-controlled crosspoint switch; prototype; scanning-electron-beam lithography system; three levels of redundancy; wafer-scale crosspoint switch design; wafer-scale system; yield analysis; yield enhancement; yield-enhanced crosspoint switch chip; Circuits; Semiconductor device measurement; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16320

Filename

16320