DocumentCode :
932548
Title :
Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs
Author :
Kumar, Jagadesh M. ; Chaudhry, Anurag
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
Volume :
51
Issue :
4
fYear :
2004
fDate :
4/1/2004 12:00:00 AM
Firstpage :
569
Lastpage :
574
Abstract :
A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.
Keywords :
MOSFET; semiconductor device models; silicon-on-insulator; surface states; work function; 2-D numerical simulation; Si-SiO2; buried oxide; channel lengths; channel region; diminished SCEs; doping concentrations; drain bias; drain-induced barrier-lowering; dual-material gate silicon-on-insulator MOSFETs; fully depleted DMG SOI MOSFET; gate metals; hot-carrier effect; short-channel effects; silicon thin film; step function; substrate bias; surface potential variation; threshold voltage; two-dimensional analytical modeling; work functions; Analytical models; Doping; Hot carrier effects; MOSFET circuits; Semiconductor process modeling; Semiconductor thin films; Silicon on insulator technology; Substrates; Threshold voltage; Two dimensional displays;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2004.823803
Filename :
1275641
Link To Document :
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