Title :
High-resolution switched-capacitor algorithmic digital-to-analogue convertor
Author_Institution :
University of Waterloo, VLSI Group, Department of Electrical Engineering, Waterloo, Canada
fDate :
10/1/1985 12:00:00 AM
Abstract :
A new high-resolution switched-capacitor algorithmic digital-to-analogue (D/A) convertor is described. It employs a novel voltage division technique to reduce errors owing to capacitor mismatch. This increases the linearity limit imposed by capacitor mismatch to 16 bits or more. The circuit possesses all the attractive features of the conventional algorithmic D/A convertors.
Keywords :
active networks; digital-analogue conversion; switched capacitor networks; algorithmic D/A convertors; capacitor mismatch; digital/analogue convertor; error reduction; high-resolution; linearity limit improvement; switched capacitor networks; voltage division technique;
Journal_Title :
Electronic Circuits and Systems, IEE Proceedings G
DOI :
10.1049/ip-g-1:19850041
