Organization of the Motorola 88110 superscalar RISC microprocessor

Motorola´s second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110´s instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described.<>