Title :
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
Author :
Rao, Lan ; Bushnell, Michael L. ; Agrawal, Vishwani D.
Author_Institution :
Sun Microsyst., Santa Clara
Abstract :
We propose a new IDDQ testing signature, the graphical IDDQ signature. We discovered that noise, in the entire set of current measurements for a chip, is a vastly superior feature for classifying chips as good or bad, compared to present methods. The measured IDDQ current as a function of vectors is defined here as the signature. We examine the shape of the waveform defined by the total set of the IDDQ measurements, to extract the number of bands that all of the current measurements cluster into, the width and separation of the bands and current glitches or noise among all IDDQ measurements. We examined the IDDQ signatures of all SEMATECH experiment chips that were classified as good or bad by a combination of functional, delay, and scan voltage tests. A single IDDQ threshold, whether absolute or differential, cannot separate good/bad chips reliably. Good chip signatures contain discrete levels (or bands) of varying widths and separations. A faulty chip almost always displays noise and glitches in the band structure. The graphical IDDQ classifier shows very high accuracy for SEMATECH test data with a test escape rate of 5.97%, compared with 7.5% for the single threshold method, 7.6% for current differences and 7.5% for the DeltaIDDQ method. The graphical IDDQ method had a 1.2% test overkill, compared with 2.3% for the single threshold method, 6.1% for current differences and 7.0% for DeltaIDDQ.
Keywords :
integrated circuit noise; integrated circuit testing; SEMATECH chips; chip signatures; current measurements; current noise; defect level reduction; graphical IDDQ signatures; integrated circuits; scan voltage tests; testing signature; threshold method; vectors function; yield loss reduction; Circuit testing; Current measurement; Delay; Integrated circuit testing; Leakage current; Noise measurement; Noise shaping; Pattern recognition; Semiconductor device measurement; Shape measurement; $I_{rm DDQ}$ testing; current noise; current signatures; data mining; pattern recognition;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.904128