Title :
Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector
Author :
Cheng, Shanfeng ; Tong, Haitao ; Silva-Martinez, Jose ; Karsilayan, Aydin Ilker
Author_Institution :
Texas A&M Univ., College Station
fDate :
6/1/2007 12:00:00 AM
Abstract :
Phase-locked loops (PLLs) using binary phase detectors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second- order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed.
Keywords :
continuous time filters; discrete time filters; phase detectors; phase locked loops; binary phase detector; first-order loop filters; most stable oscillation mode; output jitter amplitude; phase-locked loops; relative stability; second-order loop filters; steady-state analysis; transient waveform equations; Clocks; Detectors; Filters; Frequency; Jitter; Orbits; Phase detection; Phase locked loops; Steady-state; Voltage-controlled oscillators; Bang-bang phase detector (BPD); binary phase- detector; clock-and-data recovery (CDR); phase-locked loop (PLL);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2007.894429
