Title :
Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era
Author :
Lee, Jam-Wem ; Li, Yiming
Author_Institution :
Microelectron. & Inf. Syst. Res. Center, Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
5/1/2006 12:00:00 AM
Abstract :
In this paper, the floating charge effect is considered in the design of new fully silicided NMOSFETs for designing electrostatic discharge (ESD) protection circuit consisting of nanodevices. According to the designed, fabricated, and studied new fully silicided ESD protection nanodevices (e.g., 90-nm CMOS devices), our investigation demonstrates that there is a significant improvement in sustaining ESD robustness than that of the conventional fully silicided device. Furthermore, it has an excellent electrical efficiency compared with that of drain-ballast resistor-tied devices. Moreover, our novel design exhibits a higher driving current and better reliability without suffering the off-state current of the fully silicided devices. Those good characteristics are especially suitable for the output buffer design in which both driving capability and ESD robustness have to be considered.
Keywords :
MOSFET; electrostatic discharge; nanotechnology; semiconductor device models; semiconductor device reliability; CMOS devices; drain-ballast resistor-tied devices; driving current; electrical efficiency; electrostatic discharge protection circuit design; floating charge effect; fully silicided N-MOSFETs; nanodevices; off-state current; reliability; Charge measurement; Circuit synthesis; Current measurement; Electrostatic discharge; Electrostatic measurements; Fabrication; MOSFET circuits; Nanoscale devices; Protection; Robustness; Circuit design; ULSI; design; electrostatic discharge (ESD); fabrication; floating charge effect; fully silicided; measurement; nanodevice; semiconductor devices; silicide-blocked; simulation;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2006.874044