• DocumentCode
    933954
  • Title

    Fast Algorithms for Slew-Constrained Minimum Cost Buffering

  • Author

    Hu, Shiyan ; Alpert, Charles J. ; Hu, Jiang ; Karandikar, Shrirang K. ; Li, Zhuo ; Shi, Weiping ; Sze, C.N.

  • Author_Institution
    Texas A&M Univ., College Station
  • Volume
    26
  • Issue
    11
  • fYear
    2007
  • Firstpage
    2009
  • Lastpage
    2022
  • Abstract
    As a prevalent constraint, sharp slew rate is often required in circuit design, which causes a huge demand for buffering resources. This problem requires ultrafast buffering techniques to handle large volume of nets while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm using the maximum matching technique is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Fourth, buffer blockage avoidance is handled, which makes the algorithms ready for practical use. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve about 90x speedup and save up to 20% buffer area over the commonly used van Ginneken style buffering. The new algorithms also significantly outperform previous works that indirectly address the slew buffering problem.
  • Keywords
    VLSI; buffer circuits; dynamic programming; integrated circuit design; buffer blockage avoidance; circuit design; discrete buffer locations; minimum cost buffering; sharp slew rate; ultrafast buffering; van Ginneken style buffering; Application specific integrated circuits; Circuit synthesis; Constraint optimization; Costs; Degradation; Delay; Dynamic programming; Heuristic algorithms; Integrated circuit interconnections; Timing; Buffer insertion; NP-complete; input slew; interconnect; slew constraint;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2007.906477
  • Filename
    4352006