DocumentCode :
934359
Title :
Hierarchical topological sorting of apparent loops via partitioning
Author :
Beetem, John F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
Volume :
11
Issue :
5
fYear :
1992
fDate :
5/1/1992 12:00:00 AM
Firstpage :
607
Lastpage :
619
Abstract :
Topological sorting (rank ordering) is a highly useful technique for ordering a set of objects according to a precedence relation, producing an ordered list suitable for processing. Applications for topological sorting include compiled logic simulation and timing analysis. While topological sorting is easily accomplished for flat combinational logic networks, hierarchical logic can be difficult to order because feedback may appear in the hierarchical representation even though it is not present in an equivalent flattened representation. This paper presents a new general solution to this problem and describes an efficient algorithm for topological sorting even in the presence of such apparent loops. Its application to hierarchical functional simulation of combinational and synchronous sequential logic is also discussed
Keywords :
logic CAD; network topology; sorting; apparent loops; combinational logic networks; combinatorial logic; compiled logic simulation; hierarchical functional simulation; hierarchical logic; partitioning; rank ordering; sequential logic; timing analysis; topological sorting; Analytical models; Application software; Clocks; Computational modeling; Design automation; Discrete event simulation; Feedback loop; Logic; Sorting; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.127622
Filename :
127622
Link To Document :
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