DocumentCode :
934918
Title :
Iterative Decoding of Multiple-Step Majority Logic Decodable Codes
Author :
Palanki, Ravi ; Fossorier, Marc P C ; Yedidia, Jonathan S.
Author_Institution :
Qualcomm Inc., San Diego
Volume :
55
Issue :
6
fYear :
2007
fDate :
6/1/2007 12:00:00 AM
Firstpage :
1099
Lastpage :
1102
Abstract :
We investigate the performance of iterative decoding algorithms for multistep majority logic decodable (MSMLD) codes of intermediate length. We introduce a new bit-flipping algorithm that is able to decode these codes nearly as well as a maximum-likelihood decoder on the binary-symmetric channel. We show that MSMLD codes decoded using bit-flipping algorithms can outperform comparable Bose-Chaudhuri-Hocquenghem (BCH) codes decoded using standard algebraic decoding algorithms, at least for high bit-flip rates (or low and moderate signal-to-noise ratios (SNRs)).
Keywords :
block codes; iterative decoding; majority logic; maximum likelihood decoding; binary-symmetric channel; bit-flipping algorithm; bit-flipping decoding; iterative decoding; linear block codes,; majority logic decoding; maximum-likelihood decoder; multistep majority logic decodable codes; AWGN; Additive white noise; Block codes; Code standards; Iterative algorithms; Iterative decoding; Logic; Maximum likelihood decoding; Parity check codes; Signal to noise ratio; Bit flipping decoding; Bose–Chaudhuri–Hocquenghem (BCH) codes; iterative decoding; linear block codes; majority logic decoding;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/TCOMM.2007.898699
Filename :
4237471
Link To Document :
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