Area and performance comparison of pipelined RISC processors implementing different precise interrupt methods

The paper presents a comparative study of circuit area and performance degradation among four pipelined RISC processors using different precise interrupt methods. The precise interrupt methods studied in the paper include in-order completion, reorder buffer, history file and future file. The VHDL is used to model five machines at the register transfer level. The Synopsys design compiler is used to synthesise these machines as a netlist of CMOS logic gates, then gate counts are obtained. Based on the model architecture and benchmark programs, it shows that the history file method can achieve the highest performance and consume less silicon area than the reorder buffer method and the future file method.