DocumentCode :
935197
Title :
On the cusp of a validation wall
Author :
Patra, Priyadarsan
Author_Institution :
Intel, Portland
Volume :
24
Issue :
2
fYear :
2007
Firstpage :
193
Lastpage :
196
Abstract :
Traditionally, universities teach how to make or build things but not so much how to "break" things or find, patch, or prevent breaks. However, much of industry validation hinges on the latter skills. Validation is something that does not get noticed when done well, but everyone notices when something goes wrong - such as the infamous Pentium floating-point division bug. Major semiconductor companies experience postsilicon validation turning into a very expensive, time-consuming proposition, yet very few college graduates are formally trained in the area. Validation is the activity of ensuring a product satisfies its reference specifications, runs with relevant software and hardware, and meets user expectations. Here, I discuss some of the key challenges to successful validation and show why a radical transformation is necessary if validation is to be effective in the near future.
Keywords :
formal specification; formal verification; postsilicon validation; product specifications; reference specifications; Circuit testing; Computer architecture; Computer bugs; Debugging; Energy management; Fasteners; Logic; Observability; Silicon; Turning; logic; low DPM; modular validation; validation wall; virtual platform;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2007.54
Filename :
4237500
Link To Document :
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