Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits

Author

Menon, S.M. ; Jayasumana, A.P. ; Malaiya, Y.K. ; Clinkinbeard, D.R.

Author_Institution

Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

Volume

140

Issue

4

fYear

1993

fDate

7/1/1993 12:00:00 AM

Firstpage

220

Lastpage

226

Abstract

With the recent achievement of lower power and higher densities, bipolar ECL technology is expected to be used widely in high performance digital circuits. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. The paper presents a detailed analysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults between logical units without feedback and logical units with feedback in ECL are presented. An analytical approach is presented for computation of logic levels at ECL outputs under varying unknown bridging resistances. Effects of bridging faults and bridging resistances on output logic levels in ECL have been examined along with their effects on noise immunity.

Keywords

bipolar integrated circuits; circuit analysis computing; emitter-coupled logic; fault location; logic testing; bipolar ECL; bridging faults; bridging resistances; emitter-coupled logic circuits; failure mode; feedback; noise immunity; stuck-at faults;

fLanguage

English

Journal_Title

Computers and Digital Techniques, IEE Proceedings E

Publisher

iet

ISSN

0143-7062

Type

jour

Filename

232040