4×, 3-level, blind ADC-based receiver

Author

Kovacevic, N. ; Jalali, M.S. ; Liang, J. ; Ting, C. ; Sheikholeslami, A. ; Kibune, M. ; Tamura, H.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

Volume

51

Issue

7

fYear

2015

fDate

4 2 2015

Firstpage

551

Lastpage

553

Abstract

The design of a 4× blind analogue-to-digital converter (ADC)-based receiver implemented in 65 nm CMOS technology is presented. The ADC, which has three levels with two adjustable thresholds, effectively implements a speculative decision-feedback equaliser. By reducing the ADC resolution and by simplifying the digital clock and data recovery design, the power consumption is reduced by a factor of 2 compared with previous works. Measurement results confirm a bit error rate of <;10^-12 at 5 Gbit/s with a high-frequency jitter tolerance of 0.39 and 0.31 UI_pp for a 9.3 and a 12.9 dB FR4 channel, respectively. The entire receiver consumes 63 and 86 mW for the respective channels.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; clock and data recovery circuits; decision feedback equalisers; receivers; 4× 3-level blind ADC-based receiver; BER; CDR design; CMOS technology; DFE; FR4 channel; analogue-to-digital converter; bit error rate; bit rate 5 Gbit/s; digital clock and data recovery design; high-frequency jitter tolerance; power 63 mW; power 86 mW; power consumption; size 65 nm; speculative decision-feedback equaliser;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2014.4441

Filename

7073753