DocumentCode
935650
Title
Aid to hierarchial and structured logic design using temporal logic and Prolog
Author
Fujita, S. ; Kono, Susumu ; Tanaka, Hiroya ; Moto-Oka, T.
Author_Institution
University of Tokyo, Department of Electrical Engineering, Tokyo, Japan
Volume
133
Issue
5
fYear
1986
fDate
9/1/1986 12:00:00 AM
Firstpage
283
Lastpage
294
Abstract
The paper describes a study of an aid for hardware logic design using temporal logic, called linear time temporal logic (LTTL), and Prolog. A review of specification techniques for synchronisation parts using LTTL is given. A temporal logic programming language called Tokio, which is based on LTTL and includes interval variables, is presented. As parallelisms are tedious to describe sequentially in LTTL, the notion of interval variables which express a finite number of successive times is introduced.
Keywords
logic CAD; logic testing; Prolog; Tokio; hardware logic design; linear time temporal logic; logic programming language; specification techniques; structured logic design; synchronisation; temporal logic;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
DOI
10.1049/ip-e.1986.0035
Filename
4646839
Link To Document