In Situ ESD Protection Structure for Variable Operating Voltage Interface Applications in 28-nm CMOS Process

Author

Sirui Luo ; Salcedo, Javier A. ; Parthasarathy, Srinivasan ; Yuanzhong Zhou ; Hajjar, Jean-Jacques ; Liou, Juin J.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA

Volume

14

Issue

4

fYear

2014

fDate

Dec. 2014

Firstpage

1061

Lastpage

1067

Abstract

A multiple-discharge-path electrostatic discharge (ESD) cell for protecting input/output (IO) pins with a variable operating voltage (0.5-3.5 V) is presented. This device is optimized for low capacitance and synthesized with the circuit IO components for in situ ESD protection in communication interface applications developed in the 28-nm high-k metal-gate CMOS technology.

Keywords

CMOS integrated circuits; electrostatic discharge; high-k dielectric thin films; IO pins protection; circuit IO components; communication interface; high-k metal-gate CMOS technology; in situ ESD protection structure; input-output pins protection; multiple-discharge-path electrostatic discharge cell; size 28 nm; variable operating voltage interface; voltage 0.5 V to 3.5 V; Electrostatic discharges; Junctions; Logic gates; Metals; Rails; Stress; Thyristors; 28 nm CMOS; 28nm CMOS; Converters; Monolithic IO ESD Protection; converters; monolithic IO ESD protection;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2014.2364719

Filename

6934999