DocumentCode
937628
Title
State assignment scheme for two-level logic implementation based on a simulate annealing algorithm with a fast cost estimation method
Author
Lee, S.S. ; Hwang, Su Hwan
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Volume
29
Issue
18
fYear
1993
Firstpage
1625
Lastpage
1626
Abstract
A state assignment algorithm for two-level logic implementation based on a simulated annealing algorithm is proposed. To save CPU time an efficient cost estimation method is devised without losing much estimation accuracy. The experimental results based on 40 benchmark example finite state machines show that the number of cubes and area obtained by the proposed approach is approximately 10% less than that of the two-level state assignment program NOVA within a comparable CPU time. For a large example, it could reduce the number of product terms by more than 40%.
Keywords
finite state machines; logic CAD; simulated annealing; state assignment; CAD; CPU time; FSM; computer aided design; cost estimation method; simulate annealing algorithm; state assignment algorithm; two-level logic implementation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19931082
Filename
233082
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