Title :
Enhancement source-coupled logic for mixed-mode VLSI circuits
Author :
Maleki, M. ; Kiaei, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fDate :
6/1/1992 12:00:00 AM
Abstract :
Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing (ΔVL<0.2 Vdd) compared to static CMOS logic (ΔV=Vdd). For mixed-mode ICs, ESCL reduces the digital switching noise by approximately two orders of magnitude (`20-30 μA/gate) compared to conventional static logic spikes (0.5-1 mA/gate) which is essential to the development of sensitive on-chip analog circuitry. Results from several ESCL circuits implemented in a 2-μm p-well CMOS technology are presented
Keywords :
CMOS integrated circuits; VLSI; integrated logic circuits; differential ESCL topology; enhancement source-coupled logic; low-noise implementation; low-power supply noise; mixed-mode ICs; mixed-mode VLSI circuits; mixed-mode integrated circuits; p-well CMOS technology; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit noise; Circuit topology; Integrated circuit noise; Logic circuits; Noise reduction; Switching circuits; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
