Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent Variability

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V_TH shifts and fluctuations, which are even visible during the I_D-V_G tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times τ_c and τ_e, and their impact on V_TH as a function of gate voltage V_G and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V_G swing and operational temperatures.