DocumentCode :
938816
Title :
Variation-tolerant design
Author :
Bose, Pradip
Author_Institution :
IBM
Volume :
25
Issue :
2
fYear :
2005
Firstpage :
5
Lastpage :
5
Abstract :
As we introduce this year’s Hot Chips theme issue, the frequency slowdown trend that is upon us as a result of the CMOS technology outlook has to be the single major point that stands out. It is not just the per-chip power dissipation envelope that is forcing this trend, although that factor alone is perhaps the major deterrent to frequency escalation at prior (historical) rates.
Keywords :
CMOS technology; Delay estimation; Fabrication; Frequency estimation; Microarchitecture; Microprocessors; Power dissipation; Research and development; Timing; Uncertainty;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2005.40
Filename :
1453481
Link To Document :
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