Title :
Horus: large-scale symmetric multiprocessing for Opteron systems
Author :
Kota, Rajesh ; Oehler, Rich
Author_Institution :
Newisys Inc., Austin, TX, USA
Abstract :
Horus lets server vendors design up to 32-way Opteron systems. Horus is the only chip that targets the Opteron in an SMP implementation. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent hypertransport transaction.
Keywords :
cache storage; computer architecture; multiprocessing systems; multiprocessor interconnection networks; Horus; Opteron system; coherent hypertransport transaction; data cache; local directory structure; symmetric multiprocessing system; Bridges; Computer architecture; Control systems; Delay; Large-scale systems; Multiprocessing systems; Protocols; Read-write memory; Routing; Wiring; Computer System Implementation Multiprocessor Systems;
Journal_Title :
Micro, IEEE
