• DocumentCode
    938999
  • Title

    Alternative iterative digital multiplier based on cellular arrays of r.o.m.s

  • Author

    Chung, T.J. ; Bedrosian, S.D.

  • Author_Institution
    American District Telegraph Company, New York, USA
  • Volume
    12
  • Issue
    17
  • fYear
    1976
  • Firstpage
    447
  • Lastpage
    448
  • Abstract
    An alternative and even more economical iterative-array-multiplier design is presented using only half the number of r.o.m.s each half the size as our earlier version. It is shown to perform simple multiply operations with one-third saving in computation time. Thus, with a 30 ns clock, 48×48 bit multiplication takes 2.88 ¿s.
  • Keywords
    cellular arrays; multiplying circuits; read-only storage; ROM; cellular arrays; iterative digital multiplier;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19760340
  • Filename
    4240002
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=938999