DocumentCode
939804
Title
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials
Author
Imana, José L. ; Hermida, R. ; Tirado, F.
Author_Institution
Dept. of Comput. Archit. & Syst. Eng., Complutense Univ., Madrid
Volume
14
Issue
12
fYear
2006
Firstpage
1388
Lastpage
1393
Abstract
In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2m) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given. The main advantage of our design is that some of the expressions obtained are common to any irreducible polynomial, so our multiplier can be generalized to perform the multiplication over general irreducible polynomials. Moreover, the obtained expressions can be easily converted to parameterizable code using hardware description languages. The theoretical complexity analysis also shows that our bit-parallel multipliers present a reduced number of xor gates with respect to the best known results found in the literature
Keywords
Galois fields; cryptography; digital arithmetic; multiplying circuits; Galois fields; XOR gates; advanced encryption standard; bit-parallel multipliers; canonical basis; hardware description languages; irreducible pentanomials; matrix decomposition; Capacitance; Cryptography; Delay estimation; Filtering; Galois fields; Hardware; Integrated circuit interconnections; Polynomials; Runtime; Timing; Canonical basis; Galois fields; irreducible pentanomials; matrix decomposition; multiplication;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2006.887835
Filename
4052348
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