Crosstalk noise control in an SoC physical design flow

Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes signal integrity management through crosstalk noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block-, platform-, and chip-level physical design of system-on-chip designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.