• DocumentCode
    939988
  • Title

    Constrained floorplanning using network flows

  • Author

    Feng, Yan ; Mehta, Dinesh P. ; Yang, Hannah

  • Author_Institution
    Dept. of Math. & Comput. Sci., Colorado Sch. of Mines, Golden, CO, USA
  • Volume
    23
  • Issue
    4
  • fYear
    2004
  • fDate
    4/1/2004 12:00:00 AM
  • Firstpage
    572
  • Lastpage
    580
  • Abstract
    This paper presents algorithms for a constrained version of the "modern" floorplanning problem proposed by Kahng in "Classical Floorplanning Harmful?" (Kahng, 2000). Specifically, the constrained modern floorplanning problem (CMFP) is suitable when die-size is fixed, modules are permitted to have rectilinear shapes and, in addition, the approximate relative positions of the modules are known. This formulation is particularly useful in two scenarios: 1) assisting an expert floorplan architect in a semiautomated floorplan methodology and 2) in incremental floorplanning. CMFP is shown to be negative-positive hard. An algorithm based on a max-flow network formulation quickly identifies input constraints that are impossible to meet, thus permitting the floorplan architect to modify these constraints. Three algorithms [Breadth First Search (BFS), Improved BFS (IBFS), Compromise BFS (CBFS)] based on using BFS numbers to assign costs in a min-cost max-flow network formulation are presented. Experiments on standard benchmarks demonstrate that IBFS is fast and effective in practice.
  • Keywords
    circuit layout CAD; flow graphs; integrated circuit layout; minimax techniques; network routing; BFS algorithm; benchmarking; breadth first search algorithm; compromise breadth first search algorithm; constrained floorplanning; constrained modern floorplanning problem; expert floorplan architect; fixed die-size is fixed; improved breadth first search algorithm; incremental floorplanning; input constraint identification; min-cost max-flow network; negative-positive hard; network flows; rectilinear shapes; semiautomated floorplan methodology; Clocks; Context modeling; Costs; Design automation; Design methodology; Flow graphs; Packaging; Shape; Simulated annealing; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2004.825877
  • Filename
    1278534